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Freescale Semiconductor Hardware Specification
MCF5235EC Rev. 1.3, 10/2004
MCF523x Integrated Microprocessor Hardware Specification
32-bit Embedded Controller Division
The MCF523x is a family of highly-integrated 32-bit microcontrollers based on the V2 ColdFire microarchitecture. Featuring a 16 or 32 channel eTPU, 64 Kbytes of internal SRAM, a 2-bank SDRAM controller, four 32-bit timers with dedicated DMA, a 4 channel DMA controller, up to 2 CAN modules, 3 UARTs and a queued SPI, the MCF523x family has been designed for general purpose industrial control applications. It is also a high-performance upgrade for users of the MC68332. This document provides an overview of the MCF523x microcontroller family, as well as detailed descriptions of the mechanical and electrical characteristics of the devices. The MCF523x family is based on the Version 2 ColdFire reduced instruction set computing (RISC) microarchitecture operating at a core frequency of up to 150 MHz and bus frequency up to 75 MHz.
Table of Contents
1 2 3 4 5 6 7 Overview ......................................................... 1 Signal Descriptions.......................................... 9 Modes of Operation....................................... 14 Design Recommendations ............................ 17 Mechanicals/Pinouts and Part Numbers ....... 25 Preliminary Electrical Characteristics ............ 34 Documentation .............................................. 58
1
Overview
This 32-bit device's on-chip modules include:
Technical Data (c) Freescale Semiconductor, Inc., 2004. All rights reserved. * Preliminary
Overview
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V2 ColdFire core with enhanced multiply-accumulate unit (EMAC) providing 144 Dhrystone 2.1 MIPS @ 150 MHz eTPU with 16 or 32 channels, 6 Kbytes of code memory and 1.5 Kbytes of data memory with Nexus Class 1 debug support 64 Kbytes of internal SRAM External bus speed of one half the CPU operating frequencey (75 MHz bus @ 150 MHz core) 10/100 Mbps bus-mastering Ethernet controller 8 Kbytes of configurable instruction/data cache Three universal asynchronous receiver/transmitters (UARTs) Controller area network 2.0B (FlexCAN) module -- Optional second FlexCAN module multiplexed with the third UART Inter-integrated circuit (I2CTM) bus controller Queued serial peripheral interface (QSPI) module Hardware cryptography accelerator (optional) -- Random number generator -- DES/3DES/AES block cipher engine -- MD5/SHA-1/HMAC accelerator Four channel 32-bit direct memory access (DMA) controller Four channel 32-bit input capture/output compare timers with optional DMA support Four channel 16-bit periodic interrupt timers (PITs) Programmable software watchdog timer Interrupt controller capable of handling up to 126 interrupt sources Clock module with integrated phase locked loop (PLL) External bus interface module including a 2-bank synchronous DRAM controller 32-bit non-multiplexed bus with up to 8 chip select signals that support paged mode Flash memories
1.1
MCF523x Family Configurations
Table 1. MCF523x Family Configurations
Module ColdFire V2 Core with EMAC (Enhanced Multiply-Accumulate Unit) Enhanced Time Processor Unit with memory (eTPU) System Clock Performance (Dhrystone/2.1 MIPS) 5232 x 5233 x 5234 x 5235 x
16-ch 6K
32-ch 6K
16-ch 6K
32-ch 6K
up to 150 MHz up to 144
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 2 Preliminary Freescale Semiconductor
Overview
Table 1. MCF523x Family Configurations (continued)
Module Instruction/Data Cache Static RAM (SRAM) Interrupt Controllers (INTC) Edge Port Module (EPORT) External Interface Module (EIM) 4-channel Direct-Memory Access (DMA) SDRAM Controller Fast Ethernet Controller (FEC) Cryptography - Security module for data packets processing Watchdog Timer (WDT) Four Periodic Interrupt Timers (PIT) 32-bit DMA Timers QSPI UART(s) I
2C
5232
5233
5234
5235
8 Kbytes 64 Kbytes 2 x x x x -- -- x x 4 x 3 x 1 x x 2 x x x x -- -- x x 4 x 3 x 2 x x 2 x x x x x -- x x 4 x 3 x 1 x x 2 x x x x x x x x 4 x 3 x 2 x x
FlexCAN 2.0B - Controller-Area Network communication module General Purpose I/O Module (GPIO) JTAG - IEEE 1149.1 Test Access Port Package
160 QFP 256 256 256 196 MAPBGA MAPBGA MAPBGA MAPBGA
1.2
Block Diagram
The superset device in the MCF523x family comes in a 256 mold array process ball grid array (MAPBGA) package. Figure 1 shows a top-level block diagram of the MCF5235, the superset device.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 3
Overview
EIM (To/From SRAM backdoor) CHIP SELECTS
SDRAMC QSPI I2C_SDA I2C_SCL UnTXD UnRXD
Arbiter
INTC0
INTC1
EBI
UnRTS UnCTS
PADI - Pin Muxing
DTnOUT DTnIN FEC CANRX CANTX eTPU
(To/From PADI)
FAST ETHERNET CONTROLLER (FEC)
UART 0
UART 1
UART 2
I2 C
QSPI
SDRAMC
(To/From PADI) (To/From PADI)
4 CH DMA
DTIM 0
DTIM 1
DTIM 2
DTIM 3
D[31:0] A[23:0] R/W CS[3:0]
DREQ[2:0] DACK[2:0]
MUX
TA
BDM
JTAG_EN
V2 ColdFire CPU
DIV EMAC
TSIZ[1:0] TEA BS[3:0]
JTAG TAP (To/From PADI)
NEXUS
eTPU
64 Kbytes SRAM (8Kx16)x4
8 Kbytes CACHE (1Kx32)x2
PORTS (GPIO)
CIM
Watchdog Timer
(To/From Arbiter backdoor)
SKHA FlexCAN (x2) RNGA
PLL CLKGEN (To/From INTC)
PIT0
PIT1
PIT2
PIT3
MDHA Cryptography Modules
Edge Port
Figure 1. MCF5235 Block Diagram
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 4 Preliminary Freescale Semiconductor
Overview
1.3
Features
The following section gives a brief overview of this family's feature set. For more detailed information see the MCF5235 Reference Manual (MCF5235RM).
1.3.1
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Feature Overview
Version 2 ColdFire variable-length RISC processor core -- Static operation -- 32-bit address and data path on-chip -- Processor core runs at twice the bus frequency -- Sixteen general-purpose 32-bit data and address registers -- Implements the ColdFire Instruction Set Architecture, ISA_A+, with extensions to support the user stack pointer register, and 4 new instructions for improved bit processing -- Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit signal processing algorithms -- Illegal instruction decode that allows for 68K emulation support Enhanced Time Processor Unit (eTPU) -- Event triggered VLIW processor timer subsystem -- 32 channels -- 24-bit timer resolution -- 6 Kbyte of code memory and 1.5 Kbyte of data memory -- Variable number of parameters allocatable per channel -- Double match/capture channels -- Angle mode support -- DMA and interrupt request support -- Nexus Class 1 Debug support System debug support -- Integrated debug supports both ColdFire Debug and Nexus class 1 features on a single port with cross triggering operations for ease of use -- Unified programming model including both ColdFire and Nexus debug registers -- Real time trace for determining dynamic execution path -- Background debug mode (BDM) for in-circuit debugging -- Real time debug support, with two user-visible hardware breakpoint registers (PC and address with optional data) that can be configured into a 1- or 2-level trigger On-chip memories -- 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache -- 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3
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Preliminary
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Overview
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masters (e.g., DMA, FEC) Fast Ethernet Controller (FEC) -- 10 BaseT capability, half duplex or full duplex -- 100 BaseT capability, half duplex or full duplex -- On-chip transmit and receive FIFOs -- Built-in dedicated DMA controller -- Memory-based flexible descriptor rings -- Media independent interface (MII) to external transceiver (PHY) FlexCAN Modules (up to 2) -- Full implementation of the CAN protocol specification version 2.0B - Standard Data and Remote Frames (up to 109 bits long) - Extended Data and Remote Frames (up to 127 bits long) - 0-8 bytes data length - Programmable bit rate up to 1 Mbit/sec -- Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0-8 bytes data length each, configurable as Rx or Tx, all supporting standard and extended messages -- Unused MB space can be used as general purpose RAM space -- Listen only mode capability -- Content-related addressing -- Three programmable mask registers: global (for MBs 0-13), special for MB14 and special for MB15 -- Programmable transmit-first scheme: lowest ID or lowest buffer number -- "Time stamp" based on 16-bit free-running timer -- Global network time, synchronized by a specific message Three Universal Asynchronous Receiver Transmitters (UARTs) -- 16-bit divider for clock generation -- Interrupt control logic -- Maskable interrupts -- DMA support -- Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity -- Up to 2 stop bits in 1/16 increments -- Error-detection capabilities -- Modem support includes request-to-send (UnRTS) and clear-to-send (UnCTS) lines -- Transmit and receive FIFO buffers I2C Module -- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3
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Overview
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-- Fully compatible with industry-standard I2C bus -- Master or slave modes support multiple masters -- Automatic interrupt generation with programmable level Queued Serial Peripheral Interface (QSPI) -- Full-duplex, three-wire synchronous transfers -- Up to four chip selects available -- Master mode operation only -- Programmable master bit rates -- Up to 16 pre-programmed transfers Four 32-bit DMA Timers -- 13-ns resolution at 75 MHz -- Programmable sources for clock input, including an external clock option -- Programmable prescaler -- Input-capture capability with programmable trigger edge on input pin -- Output-compare with programmable mode for the output pin -- Free run and restart modes -- Maskable interrupts on input capture or reference-compare -- DMA trigger capability on input capture or reference-compare Four Periodic Interrupt Timers (PITs) -- 16-bit counter -- Selectable as free running or count down Software Watchdog Timer -- 16-bit counter -- Low power mode support Phase Locked Loop (PLL) -- Crystal or external oscillator reference -- 8 to 25 MHz reference frequency for normal PLL mode -- 24 to 75 MHz oscillator reference frequency for 2:1 mode -- Separate clock output pin Interrupt Controllers (x2) -- Support for up to 110 interrupt sources organized as follows: - 103 fully-programmable interrupt sources - 7 fixed-level external interrupt sources -- Unique vector number for each interrupt source -- Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 7
Overview
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-- Support for hardware and software interrupt acknowledge (IACK) cycles -- Combinatorial path to provide wake-up from low power modes DMA Controller -- Four fully programmable channels -- Dual-address and single-address transfer support with 8-, 16- and 32-bit data capability along with support for 16-byte (4 x 32-bit) burst transfers -- Source/destination address pointers that can increment or remain constant -- 24-bit byte transfer counter per channel -- Auto-alignment transfers supported for efficient block movement -- Bursting and cycle steal support -- Software-programmable connections between the 12 DMA requesters in the UARTs (3), 32-bit timers (4) plus external logic (4) the four DMA channels and the eTPU (1) External Bus Interface -- Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.) -- SDRAM controller supports 8-, 16-, and 32-bit wide memory devices -- Support for n-1-1-1 burst fetches from page mode Flash -- Glueless interface to SRAM devices with or without byte strobe inputs -- Programmable wait state generator -- 32-bit bidirectional data bus -- 24-bit address bus -- Up to eight chip selects available -- Byte/write enables (byte strobes) -- Ability to boot from external memories that are 8, 16, or 32 bits wide Chip Integration Module (CIM) -- System configuration during reset -- Selects one of four clock modes -- Sets boot device and its data port width -- Configures output pad drive strength -- Unique part identification number and part revision number -- Reset - Separate reset in and reset out signals - Six sources of reset: Power-on reset (POR), External, Software, Watchdog, PLL loss of clock, PLL loss of lock - Status flag indication of source of last reset General Purpose I/O interface -- Up to 142 bits of general purpose I/O
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3
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Signal Descriptions
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-- Bit manipulation supported via set/clear functions -- Unused peripheral pins may be used as extra GPIO JTAG support for system level board testing
2
Signal Descriptions
This section describes signals that connect off chip, including a table of signal properties. For a more detailed discussion of the MCF523x signals, consult the MCF5235 Reference Manual (MCF5235RM).
2.1
Signal Properties
NOTE In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A24), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality.
Table 2. MCF523x Signal Information and Muxing
Table 2 lists all of the signals grouped by function. The "Dir" column is the direction for the primary function of the pin. Refer to Section 5, "Mechanicals/Pinouts and Part Numbers," for package diagrams.
Signal Name
GPIO
Alternate 1 Alternate 2 Dir.1
MCF5232 160 QFP
MCF5232 196 MAPBGA
MCF5233 256 MAPBGA
MCF5234 256 MAPBGA
MCF5235 256 MAPBGA
Reset RESET RSTOUT -- -- -- -- -- -- I O Clock EXTAL XTAL CLKOUT -- -- -- -- -- -- -- -- -- I O O 86 85 89 M14 N14 K14 P16 R16 M16 P16 R16 M16 P16 R16 M16 83 82 N13 P13 T15 T14 T15 T14 T15 T14
Mode Selection CLKMOD[1:0] RCON -- -- -- -- -- -- I I 19,20 79 G5, H5 K10 J3, J2 P13 J3, J2 P13 J3, J2 P13
External Memory Interface and Ports
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 9
Signal Descriptions
Table 2. MCF523x Signal Information and Muxing (continued)
Signal Name A[23:21] A[20:0] GPIO PADDR[7:5] -- Alternate 1 Alternate 2 Dir.1 CS[6:4] -- -- -- O O MCF5232 160 QFP 126, 125, 124 123:115, 112:106, 102:98 MCF5232 196 MAPBGA B11, C11, D11 A12, B12, C12, A13, B13, B14, C13, C14, D12, D13, D14, E11, E12, E13, E14, F12, F13, F14, G11, G12, G13 MCF5233 256 MAPBGA B14, C14, A15 MCF5234 256 MAPBGA B14, C14, A15 MCF5235 256 MAPBGA B14, C14, A15
B15, B16, B15, B16, B15, B16, C15, C16, C15, C16, C15, C16, D16, D15, D16, D15, D16, D15, D14, E16, D14, E16, D14, E16, E15, E14, E15, E14, E15, E14, E13, F15, E13, F15, E13, F15, F14, F13, F14, F13, F14, F13, G15, G14, G15, G14, G15, G14, G13, H16, G13, H16, G13, H16, H15, H14, H15, H14, H15, H14, H13 H13 H13 K4, K3, K2, K1, L4, L3, L2, L1, M3, M2, M1, N2, N1, P2, P1, R1 K4, K3, K2, K1, L4, L3, L2, L1, M3, M2, M1, N2, N1, P2, P1, R1 K4, K3, K2, K1, L4, L3, L2, L1, M3, M2, M1, N2, N1, P2, P1, R1
D[31:16]
--
--
--
O
21:24, 26:30, G1, G2, H1, 33:39 H2, H3, H4, J1, J2, J3, J4, K1, K2, K3, K4, L1, L2 42:49,
D[15:8]
PDATAH[7:0]
--
--
O
M1, N1, M2, R2, T2, N3, R2, T2, N3, R2, T2, N3, N2, P2, L3, P3, R3, T3, P3, R3, T3, P3, R3, T3, M3, N3, N4, P4, N4, P4, N4, P4,
D[7:0]
PDATAL[7:0]
--
--
O
50:52, 56:60 P3, M4, N4, R4, T4, P5, R4, T4, P5, R4, T4, P5, P4, L5, M5, R5, N6, P6, R5, N6, P6, R5, N6, P6, N5, P5 R6, N7 R6, N7 R6, N7 143:140 63 97 -- 96 -- -- -- -- B6, C6, D7, C9, B9, A9, C9, B9, A9, C9, B9, A9, C7 A10 A10 A10 N6 H11 J14 J13 P6 P7 H13 H12 T7 K14 K13 L16 N8 P8 K16 K15 T7 K14 K13 L16 N8 P8 K16 K15 T7 K14 K13 L16 N8 P8 K16 K15
BS[3:0] OE TA TEA R/W TSIZ1 TSIZ0 TS TIP
PBS[7:4] PBUSCTL7 PBUSCTL6 PBUSCTL5 PBUSCTL4 PBUSCTL3 PBUSCTL2 PBUSCTL1 PBUSCTL0
CAS[3:0] -- -- DREQ1 -- DACK1 DACK0 DACK2 DREQ0
-- -- -- -- -- -- -- -- --
O O I I O O O O O
Chip Selects CS[7:4] CS[3:2] CS1 CS0 PCS[7:4] PCS[3:2] PCS1 -- -- SD_CS[1:0] -- -- -- -- -- -- O O O O -- 134,133 130 129 B9, A10, C10, A11 A9, C9 B10 D10 C12, A13, C13, A14 B12, D12 B13 D13 C12, A13, C13, A14 B12, D12 B13 D13 C12, A13, C13, A14 B12, D12 B13 D13
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 10 Preliminary Freescale Semiconductor
Signal Descriptions
Table 2. MCF523x Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5232 160 QFP MCF5232 196 MAPBGA MCF5233 256 MAPBGA MCF5234 256 MAPBGA MCF5235 256 MAPBGA
SDRAM Controller SD_WE SD_SCAS SD_SRAS SD_CKE SD_CS[1:0] PSDRAM5 PSDRAM4 PSDRAM3 PSDRAM2 PSDRAM[1:0] -- -- -- -- -- -- -- -- -- -- O O O O O 93 92 91 139 -- K13 K12 K11 E8 L12, L13 L13 M15 M14 C10 N15, M13 L13 M15 M14 C10 N15, M13 L13 M15 M14 C10 N15, M13
External Interrupts Port IRQ[7:3] IRQ2 IRQ1 PIRQ[7:3] PIRQ2 PIRQ1 -- DREQ2 -- -- -- -- I I I eTPU TPUCH31 TPUCH30 TPUCH29 TPUCH28 TPUCH[27:24] TPUCH23 TPUCH22 TPUCH21 TPUCH20 TPUCH[19:16] TPUCH[15:0] -- -- -- -- -- -- -- -- -- -- -- ECOL ECRS ERXCLK ERXDV ERXD[3:0] ERXER ETXCLK ETXEN ETXER ETXD[3:0] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- F3 F4 E3 E4 D3, D4, C3, C4 D5 C5 D6 C6 B6,B5, A5, B7 F2, E1, E2, D1, D2, C1, C2, B1, B2, A2, B3, A3, B4, A4, A6, A7 F1 J13 J14 -- -- -- -- -- -- -- -- -- -- F2, E1, E2, D1, D2, C1, C2, B1, B2, A2, B3, A3, B4, A4, A6, A7 F1 J13 J14 F3 F4 E3 E4 D3, D4, C3, C4 D5 C5 D6 C6 B6,B5, A5, B7 F2, E1, E2, D1, D2, C1, C2, B1, B2, A2, B3, A3, B4, A4, A6, A7 F1 J13 J14 IRQ7=64 IRQ4=65 -- 66 N7, M7, L7, R8, T8, N9, R8, T8, N9, R8, T8, N9, P8, N8 P9, R9 P9, R9 P9, R9 M8 L8 T9 N10 T9 N10 T9 N10
11, 10, 7:2, E2, E1, D1 159:154, D2, D3, C1, 152, 151 C2, B1, B2, A2, C3, B3, A3, A4, C4, BR 12 -- -- FEC E3 H10 G10
TCRCLK UTPUODIS LTPUODIS
PETPU2 PETPU1 PETPU0
-- -- --
-- -- --
EMDIO
PFECI2C2
I2C_SDA
U2RXD
I/O
--
--
--
C7
C7
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 11
Signal Descriptions
Table 2. MCF523x Signal Information and Muxing (continued)
Signal Name EMDC ECOL ECRS ERXCLK ERXDV ERXD[3:0] ERXER ETXCLK ETXEN ETXER ETXD[3:0] GPIO PFECI2C3 -- -- -- -- -- -- -- -- -- -- Alternate 1 Alternate 2 Dir.1 I2C_SCL -- -- -- -- -- -- -- -- -- -- U2TXD -- -- -- -- -- -- -- -- -- -- O I I I I I O I I O O MCF5232 160 QFP -- -- -- -- -- -- -- -- -- -- -- MCF5232 196 MAPBGA -- -- -- -- -- -- -- -- -- -- -- MCF5233 256 MAPBGA -- -- -- -- -- -- -- -- -- -- -- MCF5234 256 MAPBGA D7 F3 F4 E3 E4 MCF5235 256 MAPBGA D7 F3 F4 E3 E4
D3, D4, C3, D3, D4, C3, C4 C4 D5 C5 D6 C6 D5 C5 D6 C6
B6, B5, A5, B6, B5, A5, B7 B7
Feature Control eTPU/EthENB -- -- -- I I2C I2C_SDA I2C_SCL PFECI2C1 PFECI2C0 CAN0RX CAN0TX -- -- I/O I/O DMA DACK[2:0] and DREQ[2:0] do not have a dedicated bond pads. Please refer to the following pins for muxing: TS and DT2OUT for DACK2, TSIZ1and DT1OUT for DACK1, TSIZ0 and DT0OUT for DACK0, IRQ2 and DT2IN for DREQ2, TEA and DT1IN for DREQ1, and TIP and DT0IN for DREQ0. QSPI QSPI_CS1 QSPI_CS0 QSPI_CLK QSPI_DIN QSPI_DOUT PQSPI4 PQSPI3 PQSPI2 PQSPI1 PQSPI0 SD_CKE -- I2C_SCL I2C_SDA -- -- -- -- -- -- O O O I O UARTs U2TXD U2RXD U1CTS PUARTH1 PUARTH0 PUARTL7 CAN1TX CAN1RX U2CTS -- -- -- O I I -- -- -- A8 A7 B8 D11 D10 C11 D11 D10 C11 D11 D10 C11 -- 147 148 149 150 B7 A6 C5 B5 A5 B10 D9 B8 C8 D8 B10 D9 B8 C8 D8 B10 D9 B8 C8 D8 -- -- -- -- -- -- -- J12 J11 L15 L14 L15 L14 L15 L14 -- -- -- -- M4
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 12 Preliminary Freescale Semiconductor
Signal Descriptions
Table 2. MCF523x Signal Information and Muxing (continued)
Signal Name U1RTS U1TXD U1RXD U0CTS U0RTS U0TXD U0RXD GPIO PUARTL6 PUARTL5 PUARTL4 PUARTL3 PUARTL2 PUARTL1 PUARTL0 Alternate 1 Alternate 2 Dir.1 U2RTS CAN0TX CAN0RX -- -- -- -- -- -- -- -- -- -- -- O O I I O O I MCF5232 160 QFP -- 135 136 -- -- 14 13 MCF5232 196 MAPBGA C8 D9 D8 F3 G3 F1 F2 MCF5233 256 MAPBGA B11 A12 A11 G1 H3 H2 G2 MCF5234 256 MAPBGA B11 A12 A11 G1 H3 H2 G2 MCF5235 256 MAPBGA B11 A12 A11 G1 H3 H2 G2
DMA Timers DT3IN DT3OUT DT2IN DT2OUT DT1IN DT1OUT DT0IN DT0OUT PTIMER7 PTIMER6 PTIMER5 PTIMER4 PTIMER3 PTIMER2 PTIMER1 PTIMER0 U2CTS U2RTS DREQ2 DACK2 DREQ1 DACK1 DREQ0 DACK0 QSPI_CS2 QSPI_CS3 DT2OUT -- DT1OUT -- -- -- I O I O I O I O -- -- -- -- -- -- -- -- H14 G14 M9 L9 L6 M6 E4 F4 J15 J16 P10 R10 P7 R7 G4 G3 J15 J16 P10 R10 P7 R7 G4 G3 J15 J16 P10 R10 P7 R7 G4 G3
BDM/JTAG2 DSCLK PSTCLK BKPT DSI DSO JTAG_EN DDATA[3:0] PST[3:0] -- -- -- -- -- -- -- -- TRST TCLK TMS TDI TDO -- -- -- -- -- -- -- -- -- -- -- I O I I O I O O 70 68 71 73 72 78 -- 77:74 N9 P9 P10 M10 N10 K9 M12, N12, P12, L11 M11, N11, P11, L10 N11 T10 P11 T11 R11 N13 N14, P14, T13, R13 T12, R12, P12, N12 N11 T10 P11 T11 R11 N13 N14, P14, T13, R13 T12, R12, P12, N12 N11 T10 P11 T11 R11 N13 N14, P14, T13, R13 T12, R12, P12, N12
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 13
Modes of Operation
Table 2. MCF523x Signal Information and Muxing (continued)
Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5232 160 QFP MCF5232 196 MAPBGA MCF5233 256 MAPBGA MCF5234 256 MAPBGA MCF5235 256 MAPBGA
Test TEST PLL_TEST -- -- -- -- -- -- I I 18 -- F5 J4 R14 J4 R14 J4 R14
Power Supplies VDDPLL VSSPLL OVDD -- -- -- -- -- -- -- -- -- I I I 87 84 1, 9, 17, 32, 41, 55, 62, 69, 81, 90, 95, 105, 114, 128, 132, 138, 146 M13 L14 P15 R15
E5, E7, E6:11, F5, F7:10, F12, G5, G6, G11, E10, F7, F9, G12, H5, H6, H11, H12, J5, J6, J11, G6, G8, H7, J12, K5, K6, K11, K12, L5, L7:10, H8, H9, J6, L12, M6:M11 J8, J10, K5, K6, K8
VSS
--
--
--
I
8, 16, 25, 31, A1, A14, A1, A16, E5, E12, F6, F11, F16, 40, 54, 61, E6, E9, F6, G7:10, H7: 10, J1, J7:10, K7:10, L6, 67, 80, 88, F8, F10, L11, M5, M12, N16, T1, T6, T16 94, 104, 113, G7, G9, H6, 127, 131, J5, J7, J9, 137, 145, K7, P1, P14 153, 160 15, 53, 103, 144 D6, F11, G4, L4 A8, G16, H1, T5
VDD
--
--
--
I
NOTES: 1 Refers to pin's primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM. 2 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.
3
3.1
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Modes of Operation
Chip Configuration Mode--Device Operating Options
Chip operating mode: -- Master mode Boot device/size: -- External device boot - 32-bit - 16-bit (Default)
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Modes of Operation
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*
*
- 8-bit Output pad strength: -- Partial drive strength (Default) -- Full drive strength Clock mode: -- Normal PLL with external crystal -- Normal PLL with external clock -- 1:1 PLL Mode -- External oscillator mode (no PLL) Chip Select Configuration: -- PADDR[7:5] configured as chip select(s) and/or address line(s) - PADDR[7:5] configured as A23-A21 (default) - PADDR configured as CS6, PADDR[6:5] as A22-A21 - PADDR[7:6] configured as CS[6:5], PADDR5 as A21 - PADDR[7:5] configured as CS[6:4]
3.1.1
Chip Configuration Pins
Table 3. Configuration Pin Descriptions
Pin Chip Configuration Function Chip configuration enable Select chip operating mode Select external boot device data port size Select output pad drive strength Select clock mode Pin State/Meaning 1 Disabled 0 Enabled 1 Master 0 Reserved 00,11 External (32-bit) 10 External (8-bit) 01 External (16-bit) 1 Full 0 Partial 00 External clock mode (no VDDPLL must be supplied if a PLL PLL) mode is selected 01 1:1 PLL mode 10 Normal PLL with external clock reference 11 Normal PLL with crystal clock reference Value read defaults to 32-bit Comments Active low: if asserted, then all configuration pins must be driven appropriately for desired operation
RCON
D16 D20, D19
D21 CLKMOD1, CLKMOD0
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 15
Modes of Operation
Table 3. Configuration Pin Descriptions (continued)
Pin D25, D24 Chip Configuration Function Select chip select / address line Pin State/Meaning 00 PADDR[7:5] configured as A23-A21 (default) 10 PADDR7 configured as CS6, PADDR[6:5] as A22-A21 01 PADDR[7:6] configured as CS[6:5], PADDR5 as A21 11 PADDR[7:5] configured as CS[6:4] 0 BDM mode 1 JTAG mode Comments
JTAG_EN
Selects BDM or JTAG mode
3.2
Low Power Modes
The following features are available to support applications which require low power. * Four modes of operation: -- RUN -- WAIT -- DOZE -- STOP * Ability to shut down most peripherals independently. * Ability to shut down the external CLKOUT pin. There are four modes of operation: RUN, WAIT, DOZE, and STOP. The system enters a low power mode when the user programs the low power bits (LPMD) in the LPCR (Low Power Control Register) in the CIM before the CPU core executes a STOP instruction. This idles the CPU with no cycles active. The LPMD bits indicate to the system and clock controller to power down and stop the clocks appropriately. During STOP mode, the system clock is stopped low. A wakeup event is required to exit a low power mode and return back to RUN mode. Wakeup events consist of any of the following conditions. See the following sections for more details. 1. Any type of reset. 2. Assertion of the BKPT pin to request entry into Debug mode. 3. Debug request bit in the BDM control register to request entry into debug mode. 4. Any valid interrupt request.
3.2.1
RUN Mode
RUN mode is the normal system operating mode. Current consumption in this mode is related directly to the frequency chosen for the system clock.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 16 Preliminary Freescale Semiconductor
Design Recommendations
3.2.2
WAIT Mode
WAIT mode is intended to be used to stop only the CPU core and memory clocks until a wakeup event is detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts, which cause the CPU core to exit from WAIT mode.
3.2.3
DOZE Mode
DOZE mode affects the CPU core in the same manner as WAIT mode, but with a different code on the CIM LPMD bits, which are monitored by the peripherals. Each peripheral defines individual operational characteristics in DOZE mode. Peripherals which continue to run and have the capability of producing interrupts may cause the CPU to exit the DOZE mode and return to the RUN mode. Peripherals which are stopped will restart operation on exit from DOZE mode as defined for each peripheral.
3.2.4
STOP Mode
STOP mode affects the CPU core in the same manner as the WAIT and DOZE modes, but with a different code on the CCM LPMD bits. In this mode, all clocks to the system are stopped and the peripherals cease operation. STOP mode must be entered in a controlled manner to ensure that any current operation is properly terminated. When exiting STOP mode, most peripherals retain their pre-stop status and resume operation.
3.2.5
Peripheral Shut Down
Most peripherals may be disabled by software in order to cease internal clock generation and remain in a static state. Each peripheral has its own specific disabling sequence (refer to each peripheral description for further details). A peripheral may be disabled at anytime and will remain disabled during any low power mode of operation.
4
4.1
* * *
Design Recommendations
Layout
Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power and ground planes for the MCF523x. See application note AN1259 System Design and Layout Techniques for Noise Reduction in processor-Based Systems. Match the PC layout trace width and routing to match trace length to operating frequency and board impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace and separation. Clocks get extra separation and more precise balancing.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 17
Design Recommendations
4.2
*
Power Supply
33 F, .1 F and .01 F across each power supply
4.3
* *
Decoupling
Place the decoupling caps as close to the pins as possible, but they can be outside the footprint of the package. .1 F and .01 F at each supply input
4.4
*
Buffering
Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses when excessive loading is expected. See Section 6, "Preliminary Electrical Characteristics."
4.5
*
Pull-up Recommendations
Use external pull-up resistors on unused inputs. See pin table.
4.6
* * * * * * * *
Clocking Recommendations
Use a multi-layer board with a separate ground plane. Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator pins) as possible. Do not run a high frequency trace around crystal circuit. Ensure that the ground for the bypass capacitors is connected to a solid ground trace. Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents in the vicinity of the crystal. Tie the ground pin to the most solid ground in the system. Do not connect the trace that connects the oscillator and the ground plane to any other circuit element. This tends to make the oscillator unstable. Tie XTAL to ground when an external oscillator is clocking the device.
4.7
4.7.1
4.7.1.1
Interface Recommendations
SDRAM Controller
SDRAM Controller Signals in Synchronous Mode
Table 4 shows the behavior of SDRAM signals in synchronous mode.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 18 Preliminary Freescale Semiconductor
Design Recommendations
Table 4. Synchronous DRAM Signal Connections
Signal SD_SRAS Description Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM SD_SRAS. Do not confuse SD_SRAS with the DRAM controller's SD_CS[1:0], which should not be interfaced to the SDRAM SD_SRAS signals. Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled SD_SCAS on the SDRAM. DRAM read/write. Asserted for write operations and negated for read operations. Row address strobe. Select each memory block of SDRAMs connected to the MCF523x. One SD_CS signal selects one SDRAM block and connects to the corresponding CS signals. Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down mode where operations are suspended or they can enter self-refresh mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SD_CKE to provide command-bit functionality. Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs. Bus clock output. Connects to the CLK input of SDRAMs.
SD_SCAS
DRAMW SD_CS[1:0] SD_CKE
BS[3:0] CLKOUT
4.7.1.2
Address Multiplexing
Table 5 shows the generic address multiplexing scheme for SDRAM configurations. All possible address connection configurations can be derived from this table.
Table 5. Generic Address Multiplexing Scheme
Address Pin Row Address Column Address 17 16 15 14 13 12 11 10 9 17 18 19 20 17 16 15 14 13 12 11 10 9 17 18 19 20 0 1 2 3 4 5 6 7 8 16 17 18 19 32-bit port only 16-bit port only or 32-bit port with only 8 column address lines 16-bit port only when at least 9 column address lines are used Notes Related to Port Sizes 8-bit port only 8- and 16-bit ports only
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 19
Design Recommendations
Table 5. Generic Address Multiplexing Scheme (continued)
Address Pin Row Address Column Address 21 22 23 24 25 21 22 23 24 25 20 21 22 23 24 Notes Related to Port Sizes
The following tables provide a more comprehensive, step-by-step way to determine the correct address line connections for interfacing the MCF523x to SDRAM. To use the tables, find the one that corresponds to the number of column address lines on the SDRAM and to the port size as seen by the MCF523x, which is not necessarily the SDRAM port size. For example, if two 1M x 16-bit SDRAMs together form a 2M x 32-bit memory, the port size is 32 bits. Most SDRAMs likely have fewer address lines than are shown in the tables, so follow only the connections shown until all SDRAM address lines are connected.
Table 6. MCF523x to SDRAM Interface (8-Bit Port, 9-Column Address Lines)
MCF523x A17 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
Table 7. MCF523x to SDRAM Interface (8-Bit Port,10-Column Address Lines)
MCF523x A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 19 18 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Table 8. MCF523x to SDRAM Interface (8-Bit Port,11-Column Address Lines)
MCF523x A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 19 18 21 20 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 20 Preliminary Freescale Semiconductor
Design Recommendations
Table 9. MCF523x to SDRAM Interface (8-Bit Port,12-Column Address Lines)
MCF523x A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 19 18 21 20 23 22 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Table 10. MCF523x to SDRAM Interface (8-Bit Port,13-Column Address Lines)
MCF523x A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 19 18 21 20 23 22 25 24 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
Table 11. MCF523x to SDRAM Interface (16-Bit Port, 8-Column Address Lines)
MCF523x A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
Table 12. MCF523x to SDRAM Interface (16-Bit Port, 9-Column Address Lines)
MCF523x A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 18 17 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Table 13. MCF523x to SDRAM Interface (16-Bit Port, 10-Column Address Lines)
MCF523x A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 16 1 A0 15 2 A1 14 3 A2 13 4 A3 12 5 A4 11 6 A5 10 7 A6 9 8 A7 18 17 A8 20 19 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 21 22 23 24 25 26 27 28 29 30 31
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 21
Design Recommendations
Table 14. MCF523x to SDRAM Interface (16-Bit Port, 11-Column Address Lines)
MCF523x A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 16 1 A0 15 2 A1 14 3 A2 13 4 A3 12 5 A4 11 6 A5 10 7 A6 9 8 A7 18 17 A8 20 19 22 21 23 24 25 26 27 28 29 30 31
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Table 15. MCF523x to SDRAM Interface (16-Bit Port, 12-Column Address Lines)
MCF523x A16 A15 A14 A13 A12 A11 A10 Pins Row Column SDRAM Pins 16 1 A0 15 2 A1 14 3 A2 13 4 A3 12 5 A4 11 6 A5 10 7 A6 A9 9 8 A7 A18 A20 A22 A24 A25 A26 A27 A28 A29 A30 A31 18 17 A8 20 19 A9 22 21 24 23 25 26 27 28 29 30 31
A10 A11 A12 A13 A14 A15 A16 A17 A18
Table 16. MCF523x to SDRAM Interface (16-Bit Port, 13-Column-Address Lines)
MCF523x A16 A15 A14 A13 A12 A11 A10 Pins Row Column SDRAM Pins 16 1 A0 15 2 A1 14 3 A2 13 4 A3 12 5 A4 11 6 A5 10 7 A6 A9 9 8 A7 A18 A20 A22 A24 A26 A27 A28 A29 A30 A31 18 17 A8 20 19 A9 22 21 24 23 26 25 27 28 29 30 31
A10 A11 A12 A13 A14 A15 A16 A17
Table 17. MCF523x to SDRAM Interface (32-Bit Port, 8-Column Address Lines)
MCF523x A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 15 2 14 3 13 4 12 5 11 6 10 7 9 8 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Table 18. MCF523x to SDRAM Interface (32-Bit Port, 9-Column Address Lines)
MCF523x A15 A14 A13 A12 A11 A10 A9 A17 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 15 2 A0 14 3 A1 13 4 A2 12 5 A3 11 6 A4 10 7 A5 9 8 A6 17 16 A7 19 18 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 20 21 22 23 24 25 26 27 28 29 30 31
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 22 Preliminary Freescale Semiconductor
Design Recommendations
Table 19. MCF523x to SDRAM Interface (32-Bit Port, 10-Column Address Lines)
MCF523x A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 15 2 A0 14 3 A1 13 4 A2 12 5 A3 11 6 A4 10 7 A5 9 8 A6 17 16 A7 19 18 A8 21 20 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 22 23 24 25 26 27 28 29 30 31
Table 20. MCF523x to SDRAM Interface (32-Bit Port, 11-Column Address Lines)
MCF523x A15 A14 A13 A12 A11 A10 Pins Row Column SDRAM Pins 15 2 A0 14 3 A1 13 4 A2 12 5 A3 11 6 A4 10 7 A5 A9 9 8 A6 A17 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31 17 16 A7 19 18 A8 21 20 A9 23 22 A10 A11 A12 A13 A14 A15 A16 A17 A18 24 25 26 27 28 29 30 31
Table 21. MCF523x to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
MCF523x A15 A14 A13 A12 A11 A10 Pins Row Column SDRAM Pins 15 2 A0 14 3 A1 13 4 A2 12 5 A3 11 6 A4 10 7 A5 A9 9 8 A6 A17 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31 17 16 A7 19 18 A8 21 20 A9 23 22 25 24 26 27 28 29 30 31
A10 A11 A12 A13 A14 A15 A16 A17
4.7.1.3
SDRAM Interfacing Example
The tables in the previous section can be used to configure the interface in the following example. To interface one 2M x 32-bit x 4 bank SDRAM component (8 columns) to the MCF523x, the connections would be as shown in Table 22.
Table 22. SDRAM Hardware Connections
SDRAM Pins MCF523x Pins A0 A15 A1 A14 A2 A13 A3 A12 A4 A11 A5 A10 A6 A9 A7 A17 A8 A18 A9 A19 A10 = CMD A20 BA0 A21 BA1 A22
4.7.2
Ethernet PHY Transceiver Connection
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10 Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3 standard defines and the FEC module supports 18 signals. These are shown in Table 23.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 23
Design Recommendations
Table 23. MII Mode
Signal Description Transmit clock Transmit enable Transmit data Transmit error Collision Carrier sense Receive clock Receive enable Receive data Receive error Management channel clock Management channel serial data MCF523x Pin ETXCLK ETXEN ETXD[3:0] ETXER ECOL ECRS ERXCLK ERXDV ERXD[3:0] ERXER EMDC EMDIO
The serial mode interface operates in what is generally referred to as AMD mode. The MCF523x configuration for seven-wire serial mode connections to the external transceiver are shown in Table 24.
Table 24. Seven-Wire Mode Configuration
Signal Description Transmit clock Transmit enable Transmit data Collision Receive clock Receive enable Receive data Unused, configure as PB14 Unused input, tie to ground Unused, configure as PB[13:11] Unused output, ignore Unused, configure as PB[10:8] Unused, configure as PB15 Input after reset, connect to ground MCF523x Pin ETXCLK ETXEN ETXD[0] ECOL ERXCLK ERXDV ERXD[0] ERXER ECRS ERXD[3:1] ETXER ETXD[3:1] EMDC EMDIO
Refer to the M523xEVB evaluation board user's manual for an example of how to connect an external PHY. Schematics for this board are accessible at the MCF5235 site by navigating to: http://www.freescale.com.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 24 Preliminary Freescale Semiconductor
Mechanicals/Pinouts and Part Numbers
4.7.2.1
FlexCAN
The FlexCAN module interface to the CAN bus is composed of 2 pins: CANTX and CANRX, which are the serial transmitted data and the serial received data. The use of an external CAN transceiver to interface to the CAN bus is generally required. The transceiver is capable of driving the large current needed for the CAN bus and has current protection, against a defective CAN bus or defective stations.
4.7.3
BDM
Use the BDM interface as shown in the M523xEVB evaluation board user's manual. The schematics for this board are accessible at the MCF523x site by navigating from: http://www.freescale.com following the 32-bit Embedded Processors, 68K/ColdFire, MCF5xxx, MCF523x and M523xEVB links.
5
Mechanicals/Pinouts and Part Numbers
This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF523x devices. See Table 2 for a list the signal names and pin locations for each device.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 25
Mechanicals/Pinouts and Part Numbers
5.1
1 A VSS
Pinout--196 MAPBGA
2 TPUCH6 3 TPUCH3 4 TPUCH2 5 QSPI_ DOUT QSPI_ DIN 6 QSPI_CS0 7 U2RXD 8 U2TXD 9 CS3 10 CS6 11 CS4 12 A20 13 A17 14 VSS A
Figure 2 shows a pinout of the MCF5232CVMxxx package.
B
TPUCH8
TPUCH7
TPUCH4
TPUCH0
BS3
QSPI_CS1
U1CTS
CS7
CS1
A23
A19
A16
A15
B
C TPUCH10
TPUCH9
TPUCH5
TPUCH1 QSPI_CLK
BS2
BS0
U1RTS
CS2
CS5
A22
A18
A14
A13
C
D TPUCH13 TPUCH12 TPUCH11
NC
NC
VDD
BS1
U1RXD/ CAN0RX
U1TXD/ CAN0TX
CS0
A21
A12
A11
A10
D
E TPUCH14 TPUCH15
TCRCLK
DT0IN
OVDD
VSS
OVDD
SD_CKE
VSS
OVDD
A9
A8
A7
A6
E
F
U0TXD
U0RXD
U0CTS
DT0OUT
TEST
VSS
OVDD
VSS
OVDD
VSS
VDD
A5
A4
A3
F
G
D31
D30
U0RTS
VDD
CLKMOD1
OVDD
VSS
OVDD
VSS
LTPU ODIS UTPU ODIS
A2
A1
A0
DT3OUT
G
H
D29
D28
D27
D26
CLKMOD0
VSS
OVDD
OVDD
OVDD
TA
TIP
TS
DT3IN
H
J
D25
D24
D23
D22
VSS
OVDD
VSS
OVDD
VSS
OVDD
I2C_SCL
I2C_SDA
R/W
TEA
J
K
D21
D20
D19
D18
OVDD
OVDD
VSS
OVDD
JTAG_EN
RCON
SD_SRAS SD_SCAS
SD_WE
CLKOUT
K
L
D17
D16
D10
VDD
D3
DT1IN
IRQ5
IRQ1
DT2OUT
PST0
DDATA0
SD_CS1
SD_CS0
VSSPLL
L
M
D15
D13
D9
D6
D2
DT1OUT
IRQ6
IRQ2
DT2IN
TDI/DSI
PST3
DDATA3
VDDPLL
EXTAL
M
N
D14
D12
D8
D5
D1
OE
IRQ7
IRQ3
TRST/ DSCLK TCLK/ PSTCLK 9
TDO/DSO
PST2
DDATA2
RESET
XTAL
N
P
VSS 1
D11 2
D7 3
D4 4
D0 5
TSIZ1 6
TSIZ0 7
IRQ4 8
TMS/ BKPT 10
PST1 11
DDATA1 12
RSTOUT 13
VSS 14
P
Figure 2. MCF5232CVMxxx Pinout (196 MAPBGA)
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 26 Preliminary Freescale Semiconductor
Mechanicals/Pinouts and Part Numbers
5.2
Package Dimensions--196 MAPBGA
Figure 3 shows MCF5232CVMxxx package dimensions.
X Y
D Laser mark for pin 1 identification in this area K
M
NOTES: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M, 1994. 3. Dimension B is measured at the maximum solder ball diameter, parallel to datum plane Z. 4. Datum Z (seating plane) is defined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package.
Millimeters DIM Min Max
E
A A1 A2 b D E e S M 0.20
13X
1.32 1.75 0.27 0.47 1.18 REF 0.35 0.65 15.00 BSC 15.00 BSC 1.00 BSC 0.50 BSC
e Metalized mark for pin 1 identification in this area
A B C
S
14 13 12 11 10 9 6 5 4 3 2 1
S
13X
D E F G H J K L M N
5 A A2 0.30 Z
e
A1
Z
4
0.15 Z
Detail K Rotated 90 Clockwise
3
196X
P
b 0.30 Z X Y 0.10 Z View M-m
Figure 3. 196 MAPBGA Package Dimensions (Case No. 1128A-01)
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 27
Mechanicals/Pinouts and Part Numbers
5.2.1
Pinout--256 MAPBGA
Figure 4 through Figure 6 show pinouts of the MCF5233CVMxxx, MCF5234CVMxxx, and MCF5235CVMxxx packages.
1 A VSS 2 TPUCH6 3 TPUCH4 4 5 6 TPUCH1 7 TPUCH0 8 VDD QSPI_ CLK QSPI_ DIN QSPI_ DOUT OVDD 9 BS1 10 BS0 QSPI_ CS1 11 12 13 CS6 14 CS4 15 A21 16 VSS A
TPUCH2 TPUCH17
U1RXD/ U1TXD/ CAN0RX CAN0TX U1RTS CS3
B
TPUCH8
TPUCH7
TPUCH5
TPUCH3 TPUCH18 TPUCH19 TPUCH16 I2C_SDA/ U2RXD I2C_SCL/ U2TXD OVDD
BS2
CS1
A23
A20
A19
B
C
TPUCH10 TPUCH9 TPUCH25 TPUCH24 TPUCH22 TPUCH20
BS3
SD_CKE U1CTS
CS7
CS5
A22
A18
A17
C
D
TPUCH12 TPUCH11 TPUCH27 TPUCH26 TPUCH23 TPUCH21
QSPI_ U2RXD/ U2TXD/ CS0 CAN1RX CAN1TX OVDD OVDD OVDD
CS2
CS0
A14
A15
A16
D
E
TPUCH14 TPUCH13 TPUCH29 TPUCH28
VSS
OVDD
VSS
A10
A11
A12
A13
E
F
TCRCLK TPUCH15 TPUCH31 TPUCH30
OVDD
VSS
OVDD
OVDD
OVDD
OVDD
VSS
OVDD
A7
A8
A9
VSS
F
G
U0CTS
U0RXD
DT0OUT
DT0IN
OVDD
OVDD
VSS
VSS
VSS
VSS
OVDD
OVDD
A4
A5
A6
VDD
G
H
VDD
U0TXD CLK MOD0 D29
U0RTS CLK MOD1 D30
NC
OVDD
OVDD
VSS
VSS
VSS
VSS
OVDD
OVDD
A0 UTPU ODIS TEA
A1 LTPU ODIS TA
A2
A3
H
J
VSS
TEST
OVDD
OVDD
VSS
VSS
VSS
VSS
OVDD
OVDD
DT3IN
DT3OUT J
K
D28
D31
OVDD
OVDD
VSS
VSS
VSS
VSS
OVDD
OVDD
TIP
TS
K
L
D24
D25
D26
D27
OVDD
VSS
OVDD
OVDD
OVDD
OVDD
VSS
OVDD
SD_WE SD_ CS0 JTAG_ EN RCON
I2C_SCL/ I2C_SDA/ CAN0TX CAN0RX SD_ SRAS DDATA3 SD_ SCAS SD_CS1
R/W
L
M
D21
D22
D23
NC
VSS
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD TRST/ DSCLK TMS/ BKPT TDO/ DSO
VSS
CLKOUT M
N
D19
D20
D13
D9
NC
D3
D0
TSIZ1
IRQ5
IRQ1
PST0
VSS
N
P
D17
D18
D12
D8
D5
D2
DT1IN
TSIZ0
IRQ4
DT2IN
PST1
DDATA2 PLL_ TEST
VDDPLL
EXTAL
P
R
D16
D15
D11
D7
D4
D1
DT1OUT
IRQ7
IRQ3
DT2OUT
PST2
DDATA0
VSSPLL
XTAL
R
T
VSS 1
D14 2
D10 3
D6 4
VDD 5
VSS 6
OE 7
IRQ6 8
IRQ2 9
TCLK/ TDI/DSI PSTCLK 10 11
PST3 12
DDATA1 RSTOUT 13 14
RESET 15
VSS 16
T
Figure 4. MCF5233CVMxxx Pinout (256 MAPBGA)
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 28 Preliminary Freescale Semiconductor
Mechanicals/Pinouts and Part Numbers
1 A VSS 2 TPUCH6 3 TPUCH4 4 TPUCH2 5 ETXD1 6 TPUCH1 7 TPUCH0 8 VDD QSPI_ CLK QSPI_ DIN QSPI_ DOUT OVDD 9 BS1 10 BS0 QSPI_ CS1 11 12 13 CS6 14 CS4 15 A21 16 VSS A
U1RXD/ U1TXD/ CAN0RX CAN0TX U1RTS CS3
B
TPUCH8
TPUCH7
TPUCH5
TPUCH3
ETXD2
ETXD3
ETXD0
BS2
CS1
A23
A20
A19
B
C TPUCH10 TPUCH9
ERXD1
ERXD0
ETXCLK
ETXER
EMDIO
BS3 QSPI_ CS0 OVDD
SD_CKE U1CTS
CS7
CS5
A22
A18
A17
C
D TPUCH12 TPUCH11
ERXD3
ERXD2
ERXER
ETXEN
EMDC
U2RXD
U2TXD
CS2
CS0
A14
A15
A16
D
E TPUCH14 TPUCH13 ERXCLK
ERXDV
VSS
OVDD
OVDD
OVDD
OVDD
VSS
A10
A11
A12
A13
E
F
TCRCLK TPUCH15
ECOL
ECRS
OVDD
VSS
OVDD
OVDD
OVDD
OVDD
VSS
OVDD
A7
A8
A9
VSS
F
G
U0CTS
U0RXD
DT0OUT
DT0IN
OVDD
OVDD
VSS
VSS
VSS
VSS
OVDD
OVDD
A4
A5
A6
VDD
G
H
VDD
U0TXD CLK MOD0 D29
U0RTS CLK MOD1 D30
NC
OVDD
OVDD
VSS
VSS
VSS
VSS
OVDD
OVDD
A0 UTPU ODIS TEA
A1 LTPU ODIS TA
A2
A3
H
J
VSS
TEST
OVDD
OVDD
VSS
VSS
VSS
VSS
OVDD
OVDD
DT3IN
DT3OUT J
K
D28
D31
OVDD
OVDD
VSS
VSS
VSS
VSS
OVDD
OVDD
TIP
TS
K
L
D24
D25
D26
D27
OVDD
VSS
OVDD
OVDD
OVDD
OVDD
VSS
OVDD
SD_WE
I2C_SCL/ I2C_SDA/ CAN0TX CAN0RX SD_ SRAS DDATA3 SD_ SCAS SD_CS1
R/W
L
M
D21
D22
D23
NC
VSS
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD TRST/ DSCLK TMS/ BKPT TDO/ DSO
VSS
SD_CS0 JTAG_ EN RCON
CLKOUT M
N
D19
D20
D13
D9
NC
D3
D0
TSIZ1
IRQ5
IRQ1
PST0
VSS
N
P
D17
D18
D12
D8
D5
D2
DT1IN
TSIZ0
IRQ4
DT2IN
PST1
DDATA2 PLL_ TEST RST OUT 14
VDDPLL
EXTAL
P
R
D16
D15
D11
D7
D4
D1
DT1OUT
IRQ7
IRQ3
DT2OUT
PST2
DDATA0
VSSPLL
XTAL
R
T
VSS 1
D14 2
D10 3
D6 4
VDD 5
VSS 6
OE 7
IRQ6 8
IRQ2 9
TCLK/ TDI/DSI PSTCLK 10 11
PST3 12
DDATA1 13
RESET 15
VSS 16
T
Figure 5. MCF5234CVMxxx Pinout (256 MAPBGA)
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 29
Mechanicals/Pinouts and Part Numbers
1 A VSS 2 TPUCH6 3 TPUCH4 4 TPUCH2 5 6 7 TPUCH0 8 VDD 9 BS1 10 BS0 QSPI_ CS1 11 12 13 CS6 14 CS4 15 A21 16 VSS A
TPUCH17/ TPUCH1 ETXD1
U1RXD/ U1TXD/ CAN0RX CAN0TX U1RTS CS3
B TPUCH8 TPUCH7
TPUCH5
TPUCH3
TPUCH18/ TPUCH19/ TPUCH16/ QSPI_ ETXD2 ETXD3 ETXD0 CLK I2C_SDA/ U2RXD/ EMDIO I2C_SCL/ U2TXD/ EMDC OVDD QSPI_ DIN QSPI_ DOUT
BS2
CS1
A23
A20
A19
B
C TPUCH10 TPUCH9
TPUCH25/ TPUCH24/ TPUCH22/ TPUCH20/ ERXD1 ERXD0 ETXCLK ETXER TPUCH27/ TPUCH26/ TPUCH23/ TPUCH21/ ERXD3 ERXD2 ERXER ETXEN TPUCH29/ TPUCH2/ ERXCLK ERXDV TPUCH31/ TPUCH30/ ECOL ECRS DT0OUT DT0IN
BS3
SD_CKE U1CTS
CS7
CS5
A22
A18
A17
C
D TPUCH12 TPUCH11
QSPI_ U2RXD/ U2TXD/ CS0 CAN1RX CAN1TX
CS2
CS0
A14
A15
A16
D
E TPUCH14 TPUCH13
VSS
OVDD
OVDD
OVDD
OVDD
OVDD
VSS
A10
A11
A12
A13
E
F TCRCLK TPUCH15
OVDD
VSS
OVDD
OVDD
OVDD
OVDD
VSS
OVDD
A7
A8
A9
VSS
F
G
U0CTS
U0RXD
OVDD
OVDD
VSS
VSS
VSS
VSS
OVDD
OVDD
A4
A5
A6
VDD
G
H
VDD
U0TXD CLK MOD0 D29
U0RTS CLK MOD1 D30
NC
OVDD
OVDD
VSS
VSS
VSS
VSS
OVDD
OVDD
A0 UTPU ODIS TEA
A1 LTPU ODIS TA
A2
A3
H
J
VSS
TEST
OVDD
OVDD
VSS
VSS
VSS
VSS
OVDD
OVDD
DT3IN
DT3OUT J
K
D28
D31
OVDD
OVDD
VSS
VSS
VSS
VSS
OVDD
OVDD
TIP
TS
K
L
D24
D25
D26
D27 eTPU/ EthENB D9
OVDD
VSS
OVDD
OVDD
OVDD
OVDD
VSS
OVDD
SD_WE
I2C_SCL/ I2C_SDA/ CAN0TX CAN0RX SD_ SRAS DDATA3 SD_ SCAS SD_CS1
R/W
L
M
D21
D22
D23
VSS
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD TRST/ DSCLK TMS/ BKPT TDO/ DSO
VSS
SD_CS0 JTAG_ EN RCON
CLKOUT M
N
D19
D20
D13
NC
D3
D0
TSIZ1
IRQ5
IRQ1
PST0
VSS
N
P
D17
D18
D12
D8
D5
D2
DT1IN
TSIZ0
IRQ4
DT2IN
PST1
DDATA2 PLL_ TEST
VDDPLL
EXTAL
P
R
D16
D15
D11
D7
D4
D1
DT1OUT
IRQ7
IRQ3
DT2OUT
PST2
DDATA0
VSSPLL
XTAL
R
T
VSS 1
D14 2
D10 3
D6 4
VDD 5
VSS 6
OE 7
IRQ6 8
IRQ2 9
TCLK/ TDI/DSI PSTCLK 10 11
PST3 12
DDATA1 RSTOUT 13 14
RESET 15
VSS 16
T
Figure 6. MCF5235CVMxxx Pinout (256 MAPBGA)
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 30 Preliminary Freescale Semiconductor
Mechanicals/Pinouts and Part Numbers
5.2.2
Package Dimensions--256 MAPBGA
Figure 7 shows MCF5235CVMxxx, MCF5234CVMxxx, and MCF5233CVMxx package dimensions.
X Y
D
LASER MARK FOR PIN A1 IDENTIFICATION IN THIS AREA
M K A A2 A1 Z 4
256X
5 0.30 Z
E
0.15 Z DETAIL K
ROTATED 90CLOCKWISE NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. MILLIMETERS MIN MAX A 1.25 1.60 A1 0.27 0.47 1.16 REF A2 0.40 0.60 b 17.00 BSC D 17.00 BSC E e 1.00 BSC 0.50 BSC S
M 0.20
15X
e
METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA A B C D E F G H J K L M N P R T
S
16151413121110 7654321
15X
e
S
256X
b 0.25 0.10
3
M M
ZXY Z
DIM
VIEW M-M
Figure 7. 256 MAPBGA Package Outline
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 31
Mechanicals/Pinouts and Part Numbers
5.3
Pinout--160 QFP
VSS TPUCH7 TPUCH6 TPUCH5 TPUCH4 TPUCH3 TPUCH2 VSS TPUCH1 TPUCH0 QSPI_DOUT QSPI_DIN QSPI_CLK QSPI_CS0 OVDD VSS\OVSS VDD BS3 BS2 BS1 BS0 SD_CKE\QSPI_CS1 OVDD VSS U1RXD\CAN0RX U1TXD\CAN0TX CS3 CS2 OVDD VSS CS1 CS0 OVDD VSS A23 A22 A21 A20 A19 A18 OVDD TPUCH8 TPUCH9 TPUCH10 TPUCH11 TPUCH12 TPUCH13 VSS OVDD TPUCH14 TPUCH15 TCRCLK U0RXD U0TXD VDD VSS OVDD TEST CLKMOD1 CLKMOD0 D31 D30 D29 D28 VSS D27 D26 D25 D24 D23 VSS OVDD D22 D21 D20 D19 D18 D17 D16 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
Figure 8 shows a pinout of the MCF5232CABxxx package.
MCF5232
A17 A16 A15 A14 A13 A12 OVDD VSS A11 A10 A9 A8 A7 A6 A5 OVDD VSS/OVSS VDD A4 A3 A2 A1 A0 TA R/W OVDD VSS SD_WE SD_SCAS SD_SRAS OVDD CLKOUT VSS VDDPLL EXTAL XTAL VSSPLL RESET RSTOUT/PLL_TEST OVDD
32
OVDD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 VDD VSS\OVSS OVDD D4 D3 D2 D1 D0 VSS OVDD OE IRQ7 IRQ4 IRQ1 VSS TCLK\PSTCLK OVDD TRST\DSCLK TMS\BKPT TDO/DSO TDI/DSI PST0 PST1 PST2 PST3 JTAG_EN RCON VSS
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Figure 8. MCF5232CABxxx Pinout (160 QFP)
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Preliminary Freescale Semiconductor
Mechanicals/Pinouts and Part Numbers
5.4
Package Dimensions--160 QFP
Y L
Figure 9 shows MCF5232CAB80 package dimensions.
DS
DS
-A-, -B-, -D-
A-B S
0.20 (0.008)
0.20 (0.008)
0.20 (0.008) M
L
B
M
A-B
-A-
H
V
H
-B-
A-B
S
B
B
P G DETAIL A
DETAIL A
Z A
0.20 (0.008) M C 0.20 (0.008) A-B A-B
S
DS
BASE METAL
S
0.20 (0.008) MC A-B
S
N
DS
J F D
DETAIL C
-H-
0.13 (0.005) M
C A-B
S
DS
SECTION B-B
MILLIMETERS DIM MIN MAX A 27.90 28.10 27.90 28.10 B 3.85 3.35 C 0.22 0.38 D 3.20 3.50 E 0.22 0.33 F 0.65 BSC G H 0.25 0.35 0.11 0.23 J K 0.70 0.90 25.35 BSC L 5 16 M 0.11 0.19 N 0.325 BSC P Q 7 0 R 0.13 0.30 S 31.00 31.40 0.13 -- T U 0 -- V 31.00 31.40 0.4 -- W 1.60 REF X Y 1.33 REF 1.33 REF Z INCHES MIN MAX 1.098 1.106 1.098 1.106 0.132 1.106 0.009 0.015 0.126 0.138 0.009 0.013 0.026 REF 0.010 0.014 0.004 0.009 0.028 0.035 0.998 REF 5 16 0.004 0.007 0.013 REF 0 7 0.005 0.012 1.220 1.236 0.005 -- 0 -- 1.220 1.236 0.016 -- 0.063 REF 0.052 REF 0.052 REF
Mx
TOP & BOTTOM
NOTES 1. DIMENSIONING AND TOLERINCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER 3. DATUM PLAN -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B-, AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
Ux C E -H-
T R Qx
-C- H
W K X
0.110 (0.004)
DETAIL C
Case 864A-03
Figure 9. 160 QFP Package Dimensions
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 33
Preliminary Electrical Characteristics
5.5
Ordering Information
Table 25. Orderable Part Numbers
Freescale Part Number MCF5232CAB80 Description MCF5232 RISC Microprocessor, 160 QFP MCF5232 RISC Microprocessor, 196 MAPBGA MCF5232 RISC Microprocessor, 196 MAPBGA MCF5233 RISC Microprocessor, 256 MAPBGA MCF5233 RISC Microprocessor, 256 MAPBGA MCF5234 RISC Microprocessor, 256 MAPBGA MCF5234 RISC Microprocessor, 256 MAPBGA MCF5235 RISC Microprocessor, 256 MAPBGA MCF5235 RISC Microprocessor, 256 MAPBGA Speed 80MHz 100MHz 150MHz 100MHz 150MHz 100MHz 150MHz 100MHz 150MHz Temperature -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
MCF5232CVM100 MCF5232CVM150 MCF5233CVM100 MCF5233CVM150 MCF5234CVM100 MCF5234CVM150 MCF5235CVM100 MCF5235CVM150
6
Preliminary Electrical Characteristics
This chapter contains electrical specification tables and reference timing diagrams for the MCF5235 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5235. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. NOTE The parameters specified in this processor document supersede any values found in the module specifications.
6.1
Maximum Ratings
Table 26. Absolute Maximum Ratings1, 2
Rating Core Supply Voltage Pad Supply Voltage Clock Synthesizer Supply Voltage Digital Input Voltage
3
Symbol VDD OVDD VDDPLL VIN
Value - 0.5 to +2.0 - 0.3 to +4.0 - 0.3 to +4.0 - 0.3 to + 4.0
Unit V V V V
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 34 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 26. Absolute Maximum Ratings1, 2
Rating Instantaneous Maximum Current Single pin limit (applies to all pins) 3,4,5 Operating Temperature Range (Packaged) Storage Temperature Range Symbol ID TA (TL - TH) Tstg Value 25 - 40 to 85 - 65 to 150 Unit mA C C
NOTES: 1 Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device. 2 This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or OVDD). 3 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 All functional non-supply pins are internally clamped to V SS and OVDD. 5 Power supply must maintain regulation within operating OV DD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > OVDD) is greater than IDD, the injection current may flow out of OVDD and could result in external power supply going out of regulation. Insure external OVDD load will shunt current greater than maximum injection current. This will be the greatest risk when the processor is not consuming power (ex; no clock).Power supply must maintain regulation within operating OVDD range during instantaneous and operating maximum current conditions.
6.2
Thermal Characteristics
Table 27. Thermal Characteristics
Characteristic Symbol Four layer board (2s2p) Four layer board (2s2p) JMA JMA JB JC jt Tj 256 196 160QFP MAPBGA MAPBGA 261,2 235,6 15
7
Table 27 lists thermal resistance values
Unit C/W C/W C/W C/W C/W
o
Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature
323,4 295,6 20
8
405,6 365,6 25
9
1010 25,13 TBD
1011 25,14 TBD
1012 25,15 TBD
C
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 35
Preliminary Electrical Characteristics NOTES: 1 JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 2 Per JEDEC JESD51-6 with the board horizontal. 3 JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 4 Per JEDEC JESD51-6 with the board horizontal. 5 JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 6 Per JEDEC JESD51-6 with the board horizontal. 7 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 8 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 9 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 10 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 11 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 12 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 13 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. 14 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. 15 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in C can be obtained from:
T J = T A + ( P D x JMA ) (1)
Where: TA= Ambient Temperature, C JMA= Package Thermal Resistance, Junction-to-Ambient, C/W PD= PINT + PI/O PINT= IDD x VDD, Watts - Chip Internal Power
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 36 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
PI/O= Power Dissipation on Input and Output Pins -- User Determined For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
P D = K / ( T J + 273C ) (2)
Solving equations 1 and 2 for K gives:
K = PD x (TA + 273 C) + JMA x PD 2 (3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
6.3
DC Electrical Specifications
Table 28. DC Electrical Specifications1
Characteristic Symbol VDD OVDD VIH VIL VHYS Iin IOZ VOH VOL IAPU Cin -- -- 7 7 Min 1.35 3 0.7 x OVDD VSS - 0.3 0.06 x OVDD -1.0 -1.0 OVDD - 0.5 __ -10 Max 1.65 3.6 3.65 0.35 x OVDD -- 1.0 1.0 __ 0.5 - 130 Unit V V V V mV A A V V A pF
Core Supply Voltage Pad Supply Voltage Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Vin = VDD or VSS, Input-only pins High Impedance (Off-State) Leakage Current Vin = VDD or VSS, All input/output and output pins Output High Voltage (All input/output and all output pins) IOH = -5.0 mA Output Low Voltage (All input/output and all output pins) IOL = 5.0mA Weak Internal Pull Up Device Current, tested at VIL Max.2 Input Capacitance 3 All input-only pins All input/output (three-state) pins
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 37
Preliminary Electrical Characteristics
Table 28. DC Electrical Specifications1
Characteristic Load Capacitance4 Low drive strength High drive strength Core Operating Supply Current 5 Master Mode Pad Operating Supply Current Master Mode Low Power Modes DC Injection Current 3, 6, 7, 8 VNEGCLAMP =VSS- 0.3 V, VPOSCLAMP = VDD + 0.3 Single Pin Limit Total processor Limit, Includes sum of all stressed pins Symbol CL IDD -- OIDD -- -- IIC -1.0 -10 1.0 10 TBD TBD mA A mA TBD mA Min Max 25 50 Unit pF
NOTES: 1 Refer to Table 29 for additional PLL specifications. 2 Refer to the MCF5235 signals section for pins having weak internal pull-up devices. 3 This parameter is characterized before qualification rather than 100% tested. 4 pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces require transmission line analysis to determine proper drive strength and termination. See High Speed Signal Propagation: Advanced Black Magic by Howard W. Johnson for design guidelines. 5 Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load. 6 All functional non-supply pins are internally clamped to V SS and their respective VDD. 7 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 8 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Insure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the processor is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock is not present during the power-up sequence until the PLL has attained lock.
6.4
Oscillator and PLLMRFM Electrical Characteristics
Table 29. HiP7 PLLMRFM Electrical Specifications1
Num 1 Characteristic PLL Reference Frequency Range Crystal reference External reference 1:1 mode (NOTE: fsys/2 = 2 x fref_1:1) Core frequency CLKOUT Frequency 2 External reference On-Chip PLL Frequency Loss of Reference Frequency 3, 5 Self Clocked Mode Frequency 4, 5 Symbol Min. Value Max. Value Unit MHz fref_crystal fref_ext fref_1:1 fsys fsys/2 fLOR fSCM 0 fref / 32 100 TBD 8 8 24 25 25 75 150 75 75 1000 TBD MHz MHz MHz kHz MHz
2
3 4
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 38 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 29. HiP7 PLLMRFM Electrical Specifications1
Num 5 6 Characteristic Crystal Start-up Time 5, 6 EXTAL Input High Voltage Crystal Mode7 All other modes (Dual Controller (1:1), Bypass, External) EXTAL Input Low Voltage Crystal Mode7 All other modes (Dual Controller (1:1), Bypass, External) XTAL Output High Voltage IOH = 1.0 mA XTAL Output Low Voltage IOL = 1.0 mA XTAL Load Capacitance5 PLL Lock Time 5, 8,14 Power-up To Lock Time 5, 6,9 With Crystal Reference (includes 5 time) Without Crystal Reference10 1:1 Mode Clock Skew (between CLKOUT and EXTAL) 11 Duty Cycle of reference 5 Frequency un-LOCK Range Frequency LOCK Range CLKOUT Period Jitter, 5, 6, 9,12, 13 Measured at fsys/2 Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter (Averaged over 2 ms interval) Frequency Modulation Range Limit14, 15 (fsys/2 Max must not be exceeded) ICO Frequency. fico = fref * 2 * (MFD+2) 16 tlpll tlplk -- -- tskew tdc fUL fLCK Cjitter -- -- 5.0 .01 % fsys/2 -1 40 -3.8 -1.7 11 750 1 60 4.1 2.0 ms s ns % % fsys/2 % fsys/2 Symbol tcst VIHEXT VIHEXT Min. Value -- TBD TBD Max. Value 10 TBD TBD Unit ms V V
7
VILEXT VILEXT VOH VOL
TBD TBD TBD -- 5 --
TBD TBD -- TBD 30 750
V V V V pF s
8 9 10 11 12
13 14 15 16 17
18 19
1
Cmod fico
0.8 48
2.2 75
%fsys/2 MHz
NOTES: All values given are initial design targets and subject to change. 2 All internal registers retain data at 0 Hz. 3 "Loss of Reference Frequency" is the reference frequency detected internally, which transitions the PLL into self clocked mode. 4 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR with default MFD/RFD settings. 5 This parameter is guaranteed by characterization before qualification rather than 100% tested. 6 Proper PC board layout procedures must be followed to achieve specifications. 7 This parameter is guaranteed by design rather than 100% tested. MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 39
Preliminary Electrical Characteristics
8 9
10 11 12
13 14 15 16
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). Assuming a reference is available at power up, lock time is measured from the time VDD and VDDSYN are valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time must be added to the PLL lock time to determine the total start-up time. tlpll = (64 * 4 * 5 + 5 x ) x Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and = 1.57x10-6 x 2(MFD + 2). PLL is operating in 1:1 PLL mode. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod. Modulation percentage applies over an interval of 10s, or equivalently the modulation rate is 100KHz. Modulation rate selected must not result in fsys/2 value greater than the fsys/2 maximum specified value. Modulation range determined by hardware design. fsys/2 = fico / (2 * 2RFD)
6.5
External Interface Timing Characteristics
NOTE All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the CLKOUT output. All other timing relationships can be derived from these values.
Table 30. Processor Bus Input Timing Specifications
Table 30 lists processor bus input timings.
Name freq B0 System bus frequency CLKOUT period
Characteristic1
Symbol fsys/2 tcyc
Min 50
Max 50 1/50
Unit MHz ns
Control Inputs B1a B1b B2a B2b Control input valid to CLKOUT high BKPT valid to CLKOUT high
3 2
tCVCH tBKVCH tCHCII tBKNCH
9 9 0 0
-- -- -- --
ns ns ns ns
CLKOUT high to control inputs invalid2 CLKOUT high to asynchronous control input BKPT invalid3 Data Inputs
B4 B5
Data input (D[31:0]) valid to CLKOUT high CLKOUT high to data input (D[31:0]) invalid
tDIVCH tCHDII
4 0
-- --
ns ns
NOTES: 1 Timing specifications are tested using full drive strength pad configurations in a 50ohm transmission line environment.. 2 TEA and TA pins are being referred to as control inputs. 3 Refer to figure A-19.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 40 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Timings listed in Table 30 are shown in Figure 10 & Figure A-3.
* The timings are also valid for inputs sampled on the negative clock edge. CLKOUT(75MHz) TSETUP THOLD 1.5V
Input Setup And Hold
Invalid
1.5V Valid 1.5V
Invalid
trise Input Rise Time Vh = VIH Vl = VIL
tfall Input Fall Time Vh = VIH Vl = VIL
CLKOUT
B4 B5
Inputs
Figure 10. General Input Timing Requirements
6.6
Processor Bus Output Timing Specifications
Table 31. External Bus Output Timing Specifications
Name Characteristic Control Outputs Symbol Min Max Unit
Table 31 lists processor bus output timings.
B6a B6b B6c B7 B7a
CLKOUT high to chip selects valid
1
tCHCV tCHBV tCHOV tCHCOI tCHCI
-- -- -- 0.5tCYC+1.5 0.5tCYC+1.5
0.5tCYC +5 0.5tCYC +5 0.5tCYC +5 -- --
ns ns ns ns ns
CLKOUT high to byte enables (BS[3:0]) valid2 CLKOUT high to output enable (OE) valid3 CLKOUT high to control output (BS[3:0], OE) invalid CLKOUT high to chip selects invalid
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 41
Preliminary Electrical Characteristics
Table 31. External Bus Output Timing Specifications (continued)
Name Characteristic Symbol Min Max Unit
Address and Attribute Outputs B8 B9 CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) valid CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) invalid Data Outputs B11 B12 B13
1
tCHAV tCHAI
-- 1.5
9 --
ns ns
CLKOUT high to data output (D[31:0]) valid CLKOUT high to data output (D[31:0]) invalid CLKOUT high to data output (D[31:0]) high impedance
tCHDOV tCHDOI tCHDOZ
-- 1.5 --
9 -- 9
ns ns ns
NOTES: CS transitions after the falling edge of CLKOUT. 2 BS transitions after the falling edge of CLKOUT. 3 OE transitions after the falling edge of CLKOUT.
Read/write bus timings listed in Table 31 are shown in Figure 11, Figure 12, and Figure 13.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 42 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT B7a CSn A[23:0] TSIZ[1:0] TS TIP B8 B6c OE B7 B9 B0
B6a
B8 B8
B6a
B7a
B9
B8 B9 B8
B9 B9
R/W (H) B6b BS[3:0] D[31:0] B4 B5 TA (H) B7
B8 B6b B7 B11
B12
B13
TEA (H)
Figure 11. Read/Write (Internally Terminated) SRAM Bus Timing
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 43
Preliminary Electrical Characteristics
Figure 12 shows a bus cycle terminated by TA showing timings listed in Table 31.
S0 CLKOUT CSn B6a
B7a
S1
S2
S3
S4
S5
S0
S1
A[23:0] TSIZ[1:0]
B8
B9
B8 TS B8 TIP OE B6c B7 R/W (H) B9 B9
BS[3:0]
B6b
B7 B5 B4
D[31:0] TA B1a B2a
TEA (H)
Figure 12. SRAM Read Bus Cycle Terminated by TA
Figure 13 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 31.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 44 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
S0
CLKOUT CSn B6a
S1
S2
S3
S4
S5
S0
S1
B7a
A[23:0] TSIZ[1:0]
B8
B9
B8 TS B8 TIP OE B6c B7 B9 B9
R/W (H)
BS[3:0]
B6b
B7
D[31:0]
TA (H)
TEA
B1a
B2a
Figure 13. SRAM Read Bus Cycle Terminated by TEA
Figure 14 shows an SDRAM read cycle.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 45
Preliminary Electrical Characteristics 0 SD_CKE
D1 D3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A[23:0]
D2
Row
Column
D4
RAS
D2
D4
CAS 1
D4 D2
SDWE
D5
D6
D[31:0]
D2
RAS[1:0]
D2 D4
CAS[3:0]
ACTV 1 DACR[CASL] NOP READ NOP NOP PALL
=2
Figure 14. SDRAM Read Cycle Table 32. SDRAM Timing
NUM D1 D2 D3 D4 D5 D6 D71 D8
2
Characteristic CLKOUT high to SDRAM address valid CLKOUT high to SDRAM control valid CLKOUT high to SDRAM address invalid CLKOUT high to SDRAM control invalid SDRAM data valid to CLKOUT high CLKOUT high to SDRAM data invalid CLKOUT high to SDRAM data valid CLKOUT high to SDRAM data invalid
Symbol tCHDAV tCHDCV tCHDAI tCHDCI tDDVCH tCHDDI tCHDDVW tCHDDIW
Min -- -- 1.5 1.5 4 1.5 -- 1.5
Max 9 9 -- -- -- -- 9 --
Unit ns ns ns ns ns ns ns ns
NOTES: 1 D7 and D8 are for write cycles only.
Figure 15 shows an SDRAM write cycle.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 46 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
0 SD_CKE
D1
1
2
3
4
5
6
7
8
9
10
11
12
D3
A[23:0]
D2
Row
Column
D4
SD_SRAS
D2
SD_SCAS1
D2 D4
SD_WE
D7
D[31:0]
D2 D8
RAS[1:0]
D2 D4
CAS[3:0]
ACTV 1 DACR[CASL] NOP WRITE NOP PALL
=2
Figure 15. SDRAM Write Cycle
6.7
NUM G1 G2 G3 G4
General Purpose I/O Timing
Table 33. GPIO Timing1
Characteristic CLKOUT High to GPIO Output Valid CLKOUT High to GPIO Output Invalid GPIO Input Valid to CLKOUT High CLKOUT High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min -- 1.5 9 1.5 Max 10 -- -- -- Unit ns ns ns ns
NOTES: 1 GPIO pins include: INT, ETPU, UART, FlexCAN and Timer pins.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 47
Preliminary Electrical Characteristics
CLKOUT
G1
GPIO Outputs
G2
G3
GPIO Inputs
G4
Figure 16. GPIO Timing
6.8
Reset and Configuration Override Timing
Table 34. Reset and Configuration Override Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1
NUM R1 R2 R3 R4 R5 R6 R7 R8
Characteristic RESET Input valid to CLKOUT High CLKOUT High to RESET Input invalid RESET Input valid Time
2
Symbol tRVCH tCHRI tRIVT tCHROV tROVCV tCOS tCOH tROICZ
Min 9 1.5 5 -- 0 20 0 --
Max -- -- -- 10 -- -- -- 1
Unit ns ns tCYC ns ns tCYC ns tCYC
CLKOUT High to RSTOUT Valid RSTOUT valid to Config. Overrides valid Configuration Override Setup Time to RSTOUT invalid Configuration Override Hold Time after RSTOUT invalid RSTOUT invalid to Configuration Override High Impedance
NOTES: 1 All AC timing is shown with respect to 50% VDD levels unless otherwise noted. 2 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 48 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
CLKOUT
R1 R3
RESET
R2
R4
RSTOUT
R4 R8
R5
Configuration Overrides*: (RCON, Override pins])
R6
R7
Figure 17. RESET and Configuration Override Timing
* Refer to the Coldfire Integration Module (CIM) section for more information.
6.9
I2C Input/Output Timing Specifications
Table 35. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num I1 I2 I3 I4 I5 I6 I7 I8 I9 Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 8 -- 0 -- 4 0 2 2 Max -- -- 1 -- 1 -- -- -- -- Units tcyc tcyc ms ns ms tcyc ns tcyc tcyc
Table 35 lists specifications for the I2C input timing parameters shown in Figure 18.
Table 36 lists specifications for the I2C output timing parameters shown in Figure 18.
Table 36. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num I11 I2 I3
1 2
Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time
Min 6 10 -- 7 -- 10
Max -- -- -- -- 3 --
Units tcyc tcyc s tcyc ns tcyc
I4 1 I5 3 I6 1
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 49
Preliminary Electrical Characteristics
Table 36. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num I7 1 I8
1
Characteristic Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 2 20 10
Max -- -- --
Units tcyc tcyc tcyc
I9 1
NOTES: 1 Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 36. The I2C interface is designed to scale the actual data transition time to move it to the middle of the I2C_SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 36 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load.
Figure 18 shows timing for the values in Table 35 and Table 36.
I2 I2C_SCL I6 I5
I1
I4 I7
I8
I3
I9
I2C_SDA
Figure 18. I2C Input/Output Timings
6.10 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
6.10.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK)
The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the ERXCLK frequency. Table 37 lists MII receive channel timings.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 50 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 37. MII Receive Signal Timing
Num M1 M2 M3 M4 Characteristic ERXD[3:0], ERXDV, ERXER to ERXCLK setup ERXCLK to ERXD[3:0], ERXDV, ERXER hold ERXCLK pulse width high ERXCLK pulse width low Min 5 5 35% 35% Max -- -- 65% 65% Unit ns ns ERXCLK period ERXCLK period
Figure 19 shows MII receive signal timings listed in Table 37.
M3
ERXCLK (input)
ERXD[3:0] (inputs) ERXDV ERXER M1 M2
M4
Figure 19. MII Receive Signal Timing Diagram
6.10.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)
Table 38 lists MII transmit channel timings. The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the ETXCLK frequency. The transmit outputs (ETXD[3:0], ETXEN, ETXER) can be programmed to transition from either the rising or falling edge of ETXCLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs. Refer to the Ethernet chapter for details of this option and how to enable it.
Table 38. MII Transmit Signal Timing
Num M5 M6 M7 M8 Characteristic ETXCLK to ETXD[3:0], ETXEN, ETXER invalid ETXCLK to ETXD[3:0], ETXEN, ETXER valid ETXCLK pulse width high ETXCLK pulse width low Min 5 -- 35% 35% Max -- 25 65% 65% Unit ns ns ETXCLK period ETXCLK period
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 51
Preliminary Electrical Characteristics
Figure 20 shows MII transmit signal timings listed in Table 38.
M7
ETXCLK (input) M5 ETXD[3:0] (outputs) M8
ETXEN
ETXER M6
Figure 20. MII Transmit Signal Timing Diagram
6.10.3 MII Async Inputs Signal Timing (ECRS and ECOL)
Table 39 lists MII asynchronous inputs signal timing.
Table 39. MII Async Inputs Signal Timing
Num M9 Characteristic ECRS, ECOL minimum pulse width Min 1.5 Max -- Unit ETXCLK period
Figure 21 shows MII asynchronous input timings listed in Table 39.
ECRS, ECOL M9
Figure 21. MII Async Inputs Timing Diagram
6.10.4 MII Serial Management Channel Timing (EMDIO and EMDC)
Table 40 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
Table 40. MII Serial Management Channel Timing
Num M10 M11 M12 M13 M14 M15 Characteristic EMDC falling edge to EMDIO output invalid (minimum propagation delay) EMDC falling edge to EMDIO output valid (max prop delay) EMDIO (input) to EMDC rising edge setup EMDIO (input) to EMDC rising edge hold EMDC pulse width high EMDC pulse width low Min 0 -- 10 0 Max -- 25 -- -- Unit ns ns ns ns
40% 60% MDC period 40% 60% MDC period
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 52 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Figure 22 shows MII serial management channel timings listed in Table 40.
M14 M15
EMDC (output)
M10
EMDIO (output)
M11
EMDIO (input)
M12
M13
Figure 22. MII Serial Management Channel Timing Diagram
6.11 32-Bit Timer Module AC Timing Specifications
Table 41 lists timer module AC timings.
Table 41. Timer Module AC Timing Specifications
0-66 MHz Name T1 T2 Characteristic Min DT0IN / DT1IN / DT2IN / DT3IN cycle time DT0IN / DT1IN / DT2IN / DT3IN pulse width 3 1 Max -- -- tCYC tCYC Unit
6.12 QSPI Electrical Specifications
Table 42 lists QSPI timings.
Table 42. QSPI Modules AC Timing Specifications
Name QS1 QS2 QS3 QS4 QS5 QSPI_CS[1:0] to QSPI_CLK QSPI_CLK high to QSPI_DOUT valid. QSPI_CLK high to QSPI_DOUT invalid. (Output hold) QSPI_DIN to QSPI_CLK (Input setup) QSPI_DIN to QSPI_CLK (Input hold) Characteristic Min 1 -- 2 9 9 Max 510 10 -- -- -- Unit tcyc ns ns ns ns
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 53
Preliminary Electrical Characteristics
The values in Table 42 correspond to Figure 23.
QS1 QSPI_CS[1:0]
QSPI_CLK QS2 QSPI_DOUT QS3 QSPI_DIN QS4 QS5
Figure 23. QSPI Timing
6.13 JTAG and Boundary Scan Timing
Table 43. JTAG and Boundary Scan Timing
Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 Characteristics1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST Min DC 4 26 0 4 26 0 0 4 10 0 0 100 10 Max 1/4 3 33 33 26 8 Unit fsys/2 tCYC ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1 JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 54 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
J2 J3 J3
TCLK (input)
J4
VIH VIL J4
Figure 24. Test Clock Input Timing
TCLK
VIL J5
VIH J6
Data Inputs
J7
Input Data Valid
Data Outputs
J8
Output Data Valid
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 25. Boundary Scan (JTAG) Timing
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 55
Preliminary Electrical Characteristics
TCLK
VIL J9
VIH J10
TDI TMS
J11
Input Data Valid
TDO
J12
Output Data Valid
TDO
J11
TDO
Output Data Valid
Figure 26. Test Access Port Timing
TCLK
J14
TRST
J13
Figure 27. TRST Timing
6.14 Debug AC Timing Specifications
Table 44 lists specifications for the debug AC timing parameters shown in Figure 29.
Table 44. Debug AC Timing Specification
150 MHz Num DE0 DE1 DE2 DE3 DE4 Characteristic Min PSTCLK cycle time PST valid to PSTCLK high PSTCLK high to PST invalid DSCLK cycle time DSI valid to DSCLK high 4 1.5 5 1 Max 0.5 tcyc ns ns tcyc tcyc Units
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 56 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 44. Debug AC Timing Specification
150 MHz Num DE5 1 DE6 DE7
1
Characteristic Min DSCLK high to DSO invalid BKPT input data setup time to CLKOUT Rise CLKOUT high to BKPT high Z 4 4 0 10 Max
Units tcyc ns ns
NOTES: DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT.
Figure 28 shows real-time trace timing for the values in Table 44.
PSTCLK
DE0 DE1 DE2
PST[3:0] DDATA[3:0]
Figure 28. Real-Time Trace AC Timing
Figure 29 shows BDM serial port AC timing for the values in Table 44.
CLKOUT DE6 BKPT DE7 DE5
DSCLK DE3 DSI Current DE4 DSO Past Current Next
Figure 29. BDM Serial Port AC Timing
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 57
Documentation
7
Documentation
Table 46 lists the documents that provide a complete description of the MCF523x and their development support tools. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com.
Table 45. MCF523x Documentation
Freescale Document Number
MCF5235EC MCF5235RM MCF5235PB MCF523xFS eTPURM/D CFPRODFACT/D MCF5xxxWP MAPBGAPP CFPRM/D
Title
MCF5235 RISC Microprocessor Hardware Specifications MCF523x Reference Manual MCF523x Product Brief MCF523x Fact Sheet eTPU User Manual The ColdFire Family of 32-Bit Microprocessors Family Overview and Technology Roadmap MCF5xxxWP WHITE PAPER: Motorola ColdFire VL RISC Processors MAPBGA 4-Layer Example ColdFire Family Programmer's Reference Manual
Revision
Rev. 1.3 1 0 -- 0 0 0 0 2
Status
This document Available Available In Process Available Available under NDA Available under NDA Available Available
7.1
Document Revision History
Table 46. Document Revision History
Rev. No. 0 1 1.1 1.2 1.3 Preliminary release. -Updated Signal List table -Removed duplicate information in the module description sections. The information is all in the Signals Description Table. -Corrected Figure 8 pin 81. VDD instead of VSS -Changed instances of Motorola to Freescale -Removed detailed signal description section. This information can be found in the MCF5235RM Chapter 2. -Removed detailed feature list. This information can be found in the MCF5235RM Chapter 1. -Corrected Figure 2 pin F10. VSS instead of VDD. Change made in Table 2 as well. -Corrected Figure 8 pin 81. OVDD instead of VDD. Change made in Table 2 as well. -Cleaned up many inconsistencies within the pinout figure signal names -Corrected document IDs in Table 45 Substantive Change(s)
Table 46 provides a revision history for this document.
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 58 Preliminary Freescale Semiconductor
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MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 59
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MCF5235EC Rev. 1.3, 10/2004
* Preliminary

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